Technical Field
The present invention is generally directed to the field of packaged integrated circuit devices, and, more particularly, to a novel build-up-package for integrated circuit devices and methods of making same.
Description of the Related Art
Integrated circuit technology uses electrical devices, e.g., transistors, resistors, capacitors, etc., to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever-increasing number of linked electrical devices so that the circuit may perform its intended function. As the number of transistors increases, the integrated circuitry dimensions shrink. One challenge in the semiconductor industry is to develop improved methods for electrically connecting and packaging circuit devices which are fabricated on the same and/or on different wafers or chips. In general, it is desirable in the semiconductor industry to construct transistors which occupy less surface area on the silicon chip/die.
In the manufacture of semiconductor device assemblies, a single semiconductor die is most commonly incorporated into each sealed package. Many different package styles are used, including dual inline packages (DIP), zig-zag inline packages (ZIP), small outline J-bends (SOJ), thin small outline packages (TSOP), plastic leaded chip carriers (PLCC), small outline integrated circuits (SOIC), plastic quad flat packs (PQFP) and interdigitated leadframe (IDF). Some semiconductor device assemblies are connected to a substrate, such as a circuit board, prior to encapsulation. Manufacturers are under constant pressure to reduce the size of the packaged integrated circuit device and to increase the packaging density in packaging integrated circuit devices.
So-called build-up-packaging (BUP) is a commonly employed technique for packaging integrated circuit devices. In general, build-up-packaging involves forming a mold compound material adjacent the sides of an integrated circuit die. Typically, this is accomplished by placing a plurality of singulated die on a section of tape, with the active side of the integrated circuit die being in contact with the tape. Thereafter, mold compound material is formed in the regions between and around the plurality of die. Typically, the mold compound may take the shape of a generally circular wafer. The thickness of the mold compound is approximately the same as that of the die that are subjected to the molding process. Eventually, after subsequent processing, the packaged die are singulated by cutting the mold material to achieve the desired package size.
FIGS. 1A-1B are, respectively, a cross-sectional side view and a plan view of an illustrative integrated circuit device packaged using the build-up technique described above. The packaged integrated circuit 10 is comprised of an integrated circuit die 12, a molded body 14, a first insulating layer 16, e.g., polyimide, a layer 18 of conductive lines or traces, and a second insulating layer 20. A schematically depicted bond pad 15 is formed on the active surface 13 of the die 12. The bond pad 15 is conductively coupled to the conductive layer 18, which may sometimes be referred to as a redistribution layer. A ball pad 22 and conductive ball 24 are conductively coupled to the conductive layer 18. In FIG. 1B, the first and second insulating layers 16, 20 are not shown for purposes of clarity. Of course, it is to be understood that FIGS. 1A-1B are schematic in nature and not intended to provide every detail associated with such prior art devices.
One problem associated with integrated circuit devices packaged using such build-up techniques is there is a tendency for the conductive lines or traces that are part of the conductive layer 18 to fail or crack at or near the interface 26 between the body of the die 12 and the molded body 14 in the area indicated by the dashed-line circle in FIG. 1B. Obviously, such defects may be detrimental and perhaps fatal to the operation of the packaged integrated circuit device 10.
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.